1. Field of the Invention
The present invention generally relates to semiconductor devices and, more particularly, to a semiconductor device which is excellent in heat dissipation and is capable of effectively supply an electric power by reducing a direct-current resistance of wiring.
2. Description of the Related Art
With an increase in the number of I/O terminals formed in a semiconductor element, the power consumption of a semiconductor element tends to increase. Additionally, the package size of a semiconductor device has also been increasing due to the increase in the number of terminals. There is a fine pitch ball grid array (FBGA) type semiconductor device as a semiconductor package developed so as to solve such problems.
FIG. 1 is a cross-sectional view of a conventional fine pitch ball grid array type semiconductor device. In a conventional fine pitch ball grid array type semiconductor device, a semiconductor element 1 is mounted on a printed circuit board or a tape substrate 3 through an adhesion material 2. Electrode terminals 1a of the semiconductor element 1 are electrically connected to bonding leads 5 formed in the printed circuit board or tape substrate 3 by bonding wires 4. The semiconductor element 1 and the bonding wires 4 are encapsulated by a mold resin 6 on the printed circuit board or tape substrate 3. The bonding leads 5 and terminals formed on the printed circuit board or tape board 3 are connected to solder balls 7 serving as external connection terminals formed on the opposite side.
In the fine pitch ball grid array type semiconductor device having the above-mentioned structure, a large part of heat emitted from the semiconductor element 1 is emitted to the exterior of the semiconductor device by being transmitted through the mold resin 6, or is transmitted to the printed circuit board or tape substrate 3 through the adhesion material 2, and is emitted to the exterior of the semiconductor device from the printed circuit board or tape substrate 3. The semiconductor device using the conventional BGA (ball grid array) or PGA (pin grid array) package can be classified into tape automated bonding (TAB), wire-bonding and flip-chip bonding with respect to the connection method of a package and a semiconductor chip.
Moreover, the electrode arrangement of a semiconductor chip is roughly classified into a peripheral electrode arrangement, in which electrodes are arranged a single row or a small number of rows on the periphery of the semiconductor chip, and an area electrode arrangement, in which electrodes are arranged over the entire surface of the semiconductor chip. The combinations of the connection method and the electrode arrangement is described below.
Combination (1): Peripheral electrode arrangement+TAB connection
Combination (2): peripheral electrode arrangement+wire-bonding connection
Combination (3): area electrode arrangement+flip-chip-bonding connection
Generally (1) and (2) can make the pitch between electrodes more miniaturized as compared with (3). As of 2002, the electrode pitch to which TAB connection can respond is about 40 μm, and 40 μm (wedge wire-bonding connection) or 60 μm (ball wire-bonding connection) according to wire-bonding connection. Furthermore, in wire-bonding connection, an apparent pitch can be set to a half of the pitch at the time of a single row arrangement by locating the above-mentioned electrodes in a zigzag arrangement.
On the other hand, (3) is about 180 μm. Although the electrode pitch of a semiconductor element can be miniaturized according to 1), it needs to provide bumps (projections) such as gold on the electrodes, which may be a cause of cost increase for a large semiconductor element or a low-yield semiconductor element. Moreover, the combination of a semiconductor element and a substrate becomes one kind, thereby lacking versatility. However, when a flexible board is used as a substrate of a package, there is an advantage that bonding terminals can be formed on the substrate itself.
If it is applied to a small, high-yield semiconductor element in which wiring can be achieved with a substrate having one or two conductive layers, the semiconductor device can be at a low cost.
Since (2) has flexibility in an angle of development, (2) has advantages that an internal electrode pitch of a package substrate side can be enlarged and the selection range of substrate materials becomes wider and a plurality of semiconductor elements having different electrode arrangements can be mounted to a package substrate.
With respect to the expansion of the selection range of the substrate materials, (2) may have large advantage when a larger number of conductive layers are required than (1). Currently, (2) is a combination having positions which sandwiches (1) at a cost/performance ratio and oriented to a semiconductor element which becomes expensive when bump formation is performed by (1) as a low-cost semiconductor device having wire-bonding connections with an inexpensive substrate or a semiconductor device in which a power supply plane and ground plane are formed using a multi-layer substrate that requires a higher electric performance than (1).
In either case of (1) or (2), since a stress is applied to the electrodes of a semiconductor element when bonding connection is carried out, the above-mentioned bonding electrodes cannot be provided on an active element of the semiconductor element.
(3) has a smaller stress to electrodes than the connection according to (1) and (2) when bonding since bumps made of solder or the like are formed on the electrodes of the semiconductor element and the electrodes are connected to the package substrate by melting the bumps by heat. For this reason, an electrode for bonding can be located even on an active element of the semiconductor element. However, (3) requires time for a bonding process and an adhesion material to be filled between the semiconductor element and the package substrate so as to maintain reliability of the connection part, thereby increasing a cost as compared to (1) and (2).
As mentioned above, the combination of (3) facilitates a multi-electrode structure as compared to the peripheral electrode, and is positioned as a high-class semiconductor device which can permit the above-mentioned cost problems.
Moreover, in the conventional semiconductor device, groups of connection electrodes of the semiconductor element are connected to groups of internal electrodes of an interposer such a lead frame or a package substrate for each electrode function. In a semiconductor device, especially oriented to a commodity market, a semiconductor element is mounted in a semiconductor package such as QFP or BGA, and is connected electrically by a wire connection, a TAB connection, a bump connection, etc. From a viewpoint of production quantity, except for a part of the bump connection, an electrode arrangement of the semiconductor element mounted in a large part of semiconductor packages is a peripheral arrangement in which the electrodes for signals, the electrodes for grounding, the electrodes for internal power supply and the electrodes for external power supply are mixed.
In the above-mentioned structure, the mold resin 4 through which a heat from the semiconductor element 1 passes, the adhesion material 2 and the printed circuit board or tape substrate 3 are components formed of resin. The thermal conductivity of resin material is very low as compared with metal or the like. In view of the viewpoint of emitting the heat from the semiconductor element 1 outside efficiently, the above-mentioned structure where heat is transmitted only through resin parts have a problem that the efficiency is low.
Moreover, the bonding leads 5 formed on the printed circuit board or tape substrate 3 can be arranged only in the peripheral part of the semiconductor element 1. That is, the area where the bonding leads 5 can be arranged is restricted to the peripheral part of the semiconductor element 1, which becomes a problem when attaining high-integration by an increase in the number of terminals and miniaturization of the semiconductor device itself.
Moreover, a new problem due to miniaturization of the semiconductor element has become remarkable with respect to the lineup from a viewpoint of the above-mentioned cost/performance ratio. With evolution of the semiconductor manufacturing technology, design rules such as ASIC have miniaturized from 0.25 μm to 0.13 μm according to a reduction rule of about 70%. Moreover, a speed of device operation is increasing.
With such a miniaturization of the semiconductor manufacturing process and an increase in the speed of the semiconductor device, the timing design in consideration of the delay time of the device has become complicated. Especially the increase in a resistance R with miniaturization of wirings with respect to the semiconductor element of the peripheral electrode arrangement has caused problems such as an RC delay of a wiring portion or a logic gate delay due to an IR drop of a power supply. If the area electrode arrangement and the flip-chip bonding connection are used like the above-mentioned combination (3), it will become a large cost increase.
Furthermore, a problem of erroneous operation due to a voltage drop of an internal power supply in the center portion of the element has become notably in the semiconductor device mounting the element on which electrodes are peripherally arranged while an attempt of low-voltage operation has been progressed due to a request from market such as an elongation of a battery life of a portable equipment. In order to solve these problems, measures such as an increase in the number of internal power supply electrodes and the number of grounding terminals or an increase in the power supply/grounding layer are taken so as to specify by a simulation of a voltage drop part within the semiconductor element at the design stage of the semiconductor element and strengthening the power supply. However, such measures become cost rising factors, such as an increase in element size, a reduction in the number of the effective elements in a wafer or an increase in the number of wiring layers in the element. Moreover, even if such measures are taken, a conductive layer of a thickness of 1–2 μm can only be formed with a usual semiconductor element manufacturing process, and, thus, a direct-current resistance cannot be reduced sharply.